ASIC and FPGA design and verification
Embedded processor and System-On-Chip Archtecture and Development
Custom CAD tool design and programming
Verilog,
System Verilog, Vera, VHDL
Perl, Java, C, tcl
Synopsys Design Compiler, VCS
Altera Quartus-II, SOPC Builder, Nios
Altera
Corporation
September 2004 to present
Member of Technical Staff
Developer on SOPC Builder product, a CAD tool for automatically constructing on-chip micro networks for interconnecting IP blocks
Two Patents (pending) on technology for asynchronous clock domain crossing
Cisco Systems Inc.
March 1998 to August 2004
Joined Cisco through the acquisition of StratumOne Communications Inc. in June 1999
Hardware Engineer
As a member of the GSR 12000 Series high end router engineering team, I worked on a series of line card development projects, focusing primarily on the design of packet processing chips. These chips are complex cell-based ASICs of multi-million gate complexity which were designed in under a year each through extensive reuse of previously developed module libraries and the use of modern in-house CAD tools tailored for high level design and design reuse. These chips all have multiple asynchronous clock domains ranging in rate from 66 MHz through 622 MHz and have challenging timing constraints, which were met.
· RLDRAM-FCRAM dual-mode controller for a packet buffering and queuing system. The design featured a 400 MHz DDR interface with tight signal integrity constraints.
· Five generations of Packet-Over-SONET (POS) framer ASICs ranging from OC-3 (155 Mbps) through OC-192 (9.8 Gbps). Designed Overhead Control processor, automatic protection switching (APS), HDLC controller, SPI-4.2 and SFI-4.1 ports. Led the integration of the Quad OC-48 and the sixteen port OC-12 ASICs.
·
Developed FPGAs for line card projects:
· AOC-12/48 MPLS and ATM Transport processor implemented in Altera Stratix device family. Responsible for Egress, SPI-4.2 ports and CSR on chip bus design. This was one of the largest FPGA devices that has been developed at Cisco and presented challenging physical design and timing constraints. Data throughput rates are up to 2.4 Gbps.
· Developed several Xilinx based designs for line card “glue logic” including PCI bus and DRAM interfacing.
C-Cube Microsystems Inc.
January 1996 to July 1997
C-Cube was acquired LSI Logic Inc.
Staff VLSI Engineer
VLSI designer on the ZiVA DVD decoder product. ZIVA-3 was one of the industry’s first fully integrated DVD decoder chips. Design responsibilities included:
· core microcontroller which runs all DVD and MPEG decoding firmware
· instruction cache controller
Synopsys
Inc.
November 1990 to January 1996
Sr. R&D Engineer
VHDL Feature development on Design Compiler logic synthesis product.
Founding Engineer of the DesignWare IP product line. Development projects included:
· synthesizable arithmetic library including high speed Wallace Tree multipliers
· DSP library including biquad IIR and adaptive FIR digital filters
· DSP development environment based on VHDL links to SPW and Cossap
· optimization of VHDL compiler for DSP datapath synthesis applications
Consultant to numerous Synopsys customers engaged in DSP based ASIC designs.
Bell-Northern
Research Ltd.
June 1987 to October 1990
BNR was
the research and development subsidiary of Nortel
Ltd. –
Member of Scientific Staff
Architecture and design of programmable DSP processors for telecom systems.
Siemens AG
May 1985 to September 1986
The semiconductor division was spun out and is now known as Infineon Technologies
Engineering Intern
Development of a programmable DSP processor for high speed modems.
University
of Toronto,
B.A.Sc. in Electrical Engineering
Awarded Centennial
Thesis Prize